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LDj3SNuD
8f7fcede7f
Add Smlal_Ve, Smlsl_Ve, Smull_Ve, Umlal_Ve, Umlsl_Ve, Umull_Ve Inst.; add Tests. Add Sse Opt. for Trn1/2_V and Uzp1/2_V Inst. Nits. (#566)
* Update OpCodeTable.cs
* Update InstEmitSimdArithmetic.cs
* Update InstEmitSimdHelper.cs
* Update CpuTestSimdRegElem.cs
* Update InstEmitSimdMove.cs
* Update InstEmitSimdCvt.cs
* Update SoftFallback.cs
* Update InstEmitSimdHelper.cs
* Update SoftFloat.cs
* Update CryptoHelper.cs
* Update InstEmitSimdArithmetic.cs
* Update InstEmitSimdCmp.cs
* Address PR feedback.
* Address PR feedback.
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2019-01-29 10:54:39 -03:00 |
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Cpu
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Add Smlal_Ve, Smlsl_Ve, Smull_Ve, Umlal_Ve, Umlsl_Ve, Umull_Ve Inst.; add Tests. Add Sse Opt. for Trn1/2_V and Uzp1/2_V Inst. Nits. (#566)
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2019-01-29 10:54:39 -03:00 |
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Ryujinx.Tests.csproj
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Add Sse Opt. for S/Umax_V, S/Umin_V, S/Uaddw_V, S/Usubw_V, Fabs_S/V, Fneg_S/V Inst.; for Fcvtl_V, Fcvtn_V Inst.; and for Fcmp_S Inst.. Add/Improve other Sse Opt.. Add Tests. (#496)
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2018-11-18 00:41:16 -02:00 |