Wunk 45ce540b9b ARMeilleure: Add `gfni` acceleration (#3669) ... * ARMeilleure: Add `GFNI` detection This is intended for utilizing the `gf2p8affineqb` instruction * ARMeilleure: Add `gf2p8affineqb` Not using the VEX or EVEX-form of this instruction is intentional. There are `GFNI`-chips that do not support AVX(so no VEX encoding) such as Tremont(Lakefield) chips as well as Jasper Lake. 13df339fe7/GenuineIntel/GenuineIntel00806A1_Lakefield_LC_InstLatX64.txt (L1297-L1299) 13df339fe7/GenuineIntel/GenuineIntel00906C0_JasperLake_InstLatX64.txt (L1252-L1254) * ARMeilleure: Add `gfni` acceleration of `Rbit_V` Passes all `Rbit_V*` unit tests on my `i9-11900k` * ARMeilleure: Add `gfni` acceleration of `S{l,r}i_V` Also added a fast-path for when the shift amount is greater than the size of the element. * ARMeilleure: Add `gfni` acceleration of `Shl_V` and `Sshr_V` * ARMeilleure: Increment InternalVersion * ARMeilleure: Fix Intrinsic and Assembler Table alignment `gf2p8affineqb` is the longest instruction name I know of. It shouldn't get any wider than this. * ARMeilleure: Remove SSE2+SHA requirement for GFNI * ARMeilleure Add `X86GetGf2p8LogicalShiftLeft` Used to generate GF(2^8) 8x8 bit-matrices for bit-shifting for the `gf2p8affineqb` instruction. * ARMeilleure: Append `FeatureInfo7Ecx` to `FeatureInfo`		2022-10-02 11:17:19 +02:00
..
Assembler.cs	Add host CPU memory barriers for DMB/DSB and ordered load/store (#3015)	2022-01-21 12:47:34 -03:00
AssemblerTable.cs	ARMeilleure: Add `gfni` acceleration (#3669)	2022-10-02 11:17:19 +02:00
CallConvName.cs	…
CallingConvention.cs	Removed unused usings. (#3593)	2022-08-18 18:04:54 +02:00
CodeGenCommon.cs	…
CodeGenContext.cs	Add `Operand.Label` support to `Assembler` (#2680)	2021-10-05 14:04:55 -03:00
CodeGenerator.cs	Add host CPU memory barriers for DMB/DSB and ordered load/store (#3015)	2022-01-21 12:47:34 -03:00
HardwareCapabilities.cs	ARMeilleure: Add `gfni` acceleration (#3669)	2022-10-02 11:17:19 +02:00
IntrinsicInfo.cs	…
IntrinsicTable.cs	ARMeilleure: Add `gfni` acceleration (#3669)	2022-10-02 11:17:19 +02:00
IntrinsicType.cs	Add support for guest Fz (Fpcr) mode through host Ftz and Daz (Mxcsr) modes (fast paths). (#1630)	2020-12-07 10:37:07 +01:00
PreAllocator.cs	ARMeilleure: Hardware accelerate SHA256 (#3585)	2022-08-25 10:12:13 +00:00
X86Condition.cs	…
X86Instruction.cs	ARMeilleure: Add `gfni` acceleration (#3669)	2022-10-02 11:17:19 +02:00
X86Optimizer.cs	Add a limit on the number of uses a constant may have (#3097)	2022-02-09 17:42:47 -03:00
X86Register.cs	…