LDj3SNuD 00d4f44bbb Add Sse Opt. for S/Uaddl_V, S/Uhadd_V, S/Uhsub_V, S/Umlal_V, S/Umlsl_V, S/Urhadd_V, S/Usubl_V Inst.; and for S/Urshr_V, S/Ursra_V Inst.. (#480) ... * Update AILEmitterCtx.cs * Update AInstEmitSimdArithmetic.cs * Update AInstEmitSimdShift.cs		2018-10-25 19:10:41 -03:00
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AILBarrier.cs	Added initial support for function names from symbol table on the cpu with tracing, fix wrong ImageEnd on executables with MOD0, fix issue on the CPU on input elimination for instruction with more than one register store	2018-02-25 22:14:58 -03:00
AILBlock.cs	Added initial support for function names from symbol table on the cpu with tracing, fix wrong ImageEnd on executables with MOD0, fix issue on the CPU on input elimination for instruction with more than one register store	2018-02-25 22:14:58 -03:00
AILEmitter.cs	Add intrinsics support (#121)	2018-05-11 20:10:27 -03:00
AILEmitterCtx.cs	Add Sse Opt. for S/Uaddl_V, S/Uhadd_V, S/Uhsub_V, S/Umlal_V, S/Umlsl_V, S/Urhadd_V, S/Usubl_V Inst.; and for S/Urshr_V, S/Ursra_V Inst.. (#480)	2018-10-25 19:10:41 -03:00
AILLabel.cs	…
AILOpCode.cs	…
AILOpCodeBranch.cs	…
AILOpCodeCall.cs	…
AILOpCodeConst.cs	Initial work to support AArch32 with a interpreter, plus nvmm stubs (not used for now)	2018-05-26 17:50:47 -03:00
AILOpCodeLoad.cs	Added initial support for function names from symbol table on the cpu with tracing, fix wrong ImageEnd on executables with MOD0, fix issue on the CPU on input elimination for instruction with more than one register store	2018-02-25 22:14:58 -03:00
AILOpCodeLog.cs	…
AILOpCodeStore.cs	Added initial support for function names from symbol table on the cpu with tracing, fix wrong ImageEnd on executables with MOD0, fix issue on the CPU on input elimination for instruction with more than one register store	2018-02-25 22:14:58 -03:00
AIoType.cs	…
ALocalAlloc.cs	Improve CPU initial translation speeds (#50)	2018-03-04 14:09:59 -03:00
IAILEmit.cs	…
ILGeneratorEx.cs	Add SMAXP, SMINP, UMAX, UMAXP, UMIN and UMINP cpu instructions (#200)	2018-07-03 03:31:48 -03:00