gdkchan
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b4a1cfde10
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Add SMULL (vector), USHR (scalar), FCCMPE, FNMSUB, fixed a some instructions
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2018-02-20 14:39:03 -03:00 |
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gdkchan
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161193e113
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CPU refactoring - move SIMD (scalar and vector) instructions to separate files by category, remove AILConv and use only the methods inside SIMD helper to extract/insert vector elements
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2018-02-17 18:06:11 -03:00 |
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gdkchan
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7c314eadcf
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Emit CIL directly for more SIMD instructions, add UCVTF (vector, scalar) and UZP2, fix XTN (?)
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2018-02-15 01:32:25 -03:00 |
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gdkchan
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f68696dc4a
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Made initial implementation of the thread scheduler, refactor Svc to avoid passing many arguments
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2018-02-13 23:43:08 -03:00 |
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gdkchan
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7d11a146c0
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Generate CIL for SCVTF (vector), add undefined encodings for some instructions
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2018-02-12 00:37:20 -03:00 |
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gdkchan
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ccc9ce1908
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Move a few more SIMD instructions to emit CIL directly instead of a method call
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2018-02-09 17:14:47 -03:00 |
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gdkchan
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6a3aa6cd88
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Add FVCTZS (fixed point variant) and LD1 (single structure variant) instructions
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2018-02-09 00:26:20 -03:00 |
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gdkchan
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18ac1c4045
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Removed parts of the MMU functionality to use memory directly (faster, but potentially more dangerous, WIP), also changed the Shl/Sshr immediate instructions to use IL instead of calling the method
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2018-02-07 13:44:48 -03:00 |
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gdkchan
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b7e1d9930d
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aloha
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2018-02-04 20:08:20 -03:00 |