1 Commits (52d6f2e656c21c3e6693df93a3f09cd2e6a4e40e)

Author	SHA1	Message	Date
merry	7b35ebc64a	T32: Implement ALU (shifted register) instructions (#3135) ... * T32: Implement ADC, ADD, AND, BIC, CMN, CMP, EOR, MOV, MVN, ORN, ORR, RSB, SBC, SUB, TEQ, TST (shifted register) * OpCodeTable: Sort T32 list * Tests: Rename RandomTestCase to PrecomputedThumbTestCase * T32: Tests for AluRsImm instructions * fix nit * fix nit 2	2022-02-22 19:11:28 -03:00